Integrated circuit manufacturers have relied an two principal approaches to improving integrated circuit chip performance relating to speed and stand-by leakage current (Iddq). Device regions, such as source and drain regions in a MOS transistor device are formed by implanting dopants into a semiconductor substrate. In one approach, the implant energy (and thus implant depth) and/or implant dosage of the implantation step used to form these device regions is adjusted to change the doping profile of the MOS devices in the IC, thereby optimizing the transistors' DC and AC parameters. In a second approach, other design or process parameters, such as materials, thermal budget, etc. are modified or adjusted to obtain the desired IC chip performance.
Changing the dopant profile can result in significant DC/AC parametric changes. This approach is unacceptable for existing products that cannot afford SPICE model changes to the silicon. Changing other parameters, such as materials, thermal budget, etc., usually leads to increased cost and cycle time and can require circuit redesign, all of which are undesirable.
Methods for enhancing device performance are desired.